To increase the density of devices using integrated circuit chips it is desirable to allow interconnections to be made to both the top and bottom surfaces of the integrated circuit chip. This requires formation of through silicon vias from the top to the bottom surface of the integrated chip that are compatible with complementary metal oxide silicon (CMOS) technology. Many existing through via schemes are either difficult to integrate into CMOS fabrication processes or result in unacceptable degradation of signals propagating from/to the front surface of the integrated circuit chip to/from the bottom surface of the integrated circuit chip. Accordingly, there exists a need in the art to overcome the deficiencies and limitations described hereinabove.